Title :
Security evaluation of dual rail logic against DPA attacks
Author :
Razafindraibe, A. ; Maurine, P. ; Robert, M. ; Renaudin, M.
Author_Institution :
Dept. of Microelectron., LIRMM, Montpellier
Abstract :
Based on a first order model of the switching current flowing in CMOS cell, an investigation of the robustness against DPA attacks of dual rail logic is carried out. The result of this investigation, performed on 130nm process, is the formal identification of the design range in which dual rail logic can be considered as robust
Keywords :
CMOS logic circuits; logic design; security of data; 130 nm; CMOS cell; DPA attacks; dual rail logic; first order model; security evaluation; switching current; CMOS logic circuits; Cryptography; Encoding; Energy consumption; Logic design; Microelectronics; Rails; Robustness; Security; Semiconductor device modeling;
Conference_Titel :
Very Large Scale Integration, 2006 IFIP International Conference on
Conference_Location :
Nice
Print_ISBN :
3-901882-19-7
DOI :
10.1109/VLSISOC.2006.313230
