High Speed Area Efficient Multi-resolution 2-D 9/7 filter DWT Processor

An efficient architecture for a multi-resolution symmetrically extended 2D 9/7 filter discrete wavelet transform processor is presented in this paper. Hardware complexity is greatly reduced with improved performance, thanks to the proposed combination of lifting scheme and line based architecture. Synthesizing the proposed design on a Xilinx Virtex 2, we achieve a frequency of operation as high as 171.8 MHz and a very low CLB slice count of 340 slices for level one transformation of 128-by-128 pixel test image of Lena. These figures compare very favorably with other architectures reported so far. The architecture has been successfully verified by testbench simulation using ModelSim