Title :
A 6.35Mbps 1024-bit RSA crypto coprocessor in a 0.18um CMOS technology
Author :
Zhao, Xuemi ; Wang, Zhiying ; Lu, Hongyi ; Dai, Kui
Author_Institution :
Sch. of Comput., National Univ. of Defense Technol., Changsha
Abstract :
In this paper a RSA crypto coprocessor that is fabricated using a 0.18mum CMOS technology is presented. This processor combines a new version of high radix Montgomery multiplication algorithm with a super-pipeline design. With this algorithm, modular exponentiation can be decomposed into a series of primitive operation (PO) matrixes. All the POs are scheduled on the pipeline by employing column-sharing strategy, and inside the PO all the partial results are compressed first by Wallace tree to assure only one carry propagation in the critical path. With these optimizations, a decryption rate of 6.35 Mbps can be achieved for 1024-bit RSA
Keywords :
CMOS integrated circuits; coprocessors; cryptography; 0.18 micron; 6.35 Mbit/s; CMOS technology; Montgomery multiplication algorithm; RSA crypto coprocessor; Wallace tree; modular exponentiation; primitive operation; super pipeline design; Acceleration; Algorithm design and analysis; Application specific integrated circuits; CMOS technology; Cathode ray tubes; Coprocessors; Field programmable gate arrays; Hardware; Pipelines; Public key cryptography;
Conference_Titel :
Very Large Scale Integration, 2006 IFIP International Conference on
Conference_Location :
Nice
Print_ISBN :
3-901882-19-7
DOI :
10.1109/VLSISOC.2006.313236
