Title :
Parallel counter implementation
Author :
Jones, Robert F., Jr. ; Swartzlander, Earl E., Jr.
Author_Institution :
Adv. Micro Devices Inc., Austin, TX, USA
Abstract :
An (n,m) parallel counter is a circuit with n inputs that produces an m-bit binary count of the number of its inputs that are ones. The design of large parallel counters with up to 1022 inputs is reported. Design tradeoffs regarding the use of counter cells of size ranging from (3,2) to (31,5) as building blocks are examined
Keywords :
counting circuits; digital arithmetic; logic design; (n,m) counter; design tradeoffs; m-bit binary count; n inputs; parallel counter; Adders; Area measurement; Capacitance; Counting circuits; Delay estimation; Integrated circuit interconnections; Libraries; Logic design; Measurement standards; Neural networks;
Conference_Titel :
Signals, Systems and Computers, 1992. 1992 Conference Record of The Twenty-Sixth Asilomar Conference on
Conference_Location :
Pacific Grove, CA
Print_ISBN :
0-8186-3160-0
DOI :
10.1109/ACSSC.1992.269170
