Title :
An improved architecture for column compression multipliers
Author :
Wang, Zhen ; Jullien, G.A. ; Miller, W.C.
Author_Institution :
Windsor Univ., Ont., Canada
Abstract :
Multipliers built with column-compression (CC) techniques, using full and half adders, are reexamined. Constraints for column compression are analyzed, and, under these constraints, considerable flexibility for the realization of a new CC multiplier architecture is exposed. Using the example of an 8-b×8-b CC multiplier, it is shown that this new architecture is more area efficient and has shorter interconnections than the Dadda multiplier
Keywords :
adders; digital arithmetic; logic design; multiplying circuits; Dadda multiplier; area efficient; column compression multipliers; full adders; half adders; multiplier architecture; shorter interconnections; Area measurement; Buildings; Compressors; Counting circuits; Delay effects; Equations; Telecommunications; Very large scale integration; Wiring;
Conference_Titel :
Signals, Systems and Computers, 1992. 1992 Conference Record of The Twenty-Sixth Asilomar Conference on
Conference_Location :
Pacific Grove, CA
Print_ISBN :
0-8186-3160-0
DOI :
10.1109/ACSSC.1992.269174
