DocumentCode
1586514
Title
Fast multiplier bit-product matrix reduction using bit-ordering and parity generaton
Author
Drerup, Ben C. ; Swartzlander, Earl E., Jr.
Author_Institution
IBM Corp., Austin, TX, USA
fYear
1992
Firstpage
356
Abstract
The Wallace tree/Dadda fast multiplier consists of the three steps: (1) form a bit-product matrix; (2) reduce the bit-product matrix to two rows; and (3) sum the two rows. An approach for implementing the second step using bit-ordering and parity generation logic is described. This is very different from the Wallace/Dadda method, which uses full and half adders to reduce the bit-product matrix. The approach yields a multiplier that is faster than a Wallace-Dadda multiplier when multiplying small numbers. However, it also requires more gates to implement
Keywords
digital arithmetic; logic design; multiplying circuits; Wallace-Dadda multiplier; bit-ordering; bit-product matrix reduction; fast multiplier; parity generation logic; Added delay; Clocks; Counting circuits; Hardware; Logic; Out of order; Pulse inverters; Sorting;
fLanguage
English
Publisher
ieee
Conference_Titel
Signals, Systems and Computers, 1992. 1992 Conference Record of The Twenty-Sixth Asilomar Conference on
Conference_Location
Pacific Grove, CA
ISSN
1058-6393
Print_ISBN
0-8186-3160-0
Type
conf
DOI
10.1109/ACSSC.1992.269175
Filename
269175
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