Title :
Organic Computing at the System on Chip Level
Author :
Bouajila, A. ; Zeppenfeld, J. ; Stechele, W. ; Herkersdorf, A. ; Bernauer, A. ; Bringmann, O. ; Rosenstiel, W.
Author_Institution :
Inst. for Integrated Syst., Munich Univ. of Technol.
Abstract :
The evolution of CMOS technologies leads to integrated circuits with ever smaller device sizes, lower supply voltage, higher clock frequency and more process variability. Intermittent faults effecting logic and timing are becoming a major challenge for future integrated circuit designs. This paper presents an organic computing inspired SoC architecture which applies self-organization and self-calibration concepts to build reliable SoCs with lower overheads and a broader fault coverage than classical fault-tolerance techniques. We demonstrate the feasibility of this approach by example on the processing pipeline of a public-domain RISC CPU core
Keywords :
microprocessor chips; reduced instruction set computing; system-on-chip; CMOS technologies; SoC architecture; fault coverage; future integrated circuit designs; intermittent faults; pipeline processing; public-domain RISC CPU core; self-calibration concepts; self-organization architecture; system on chip organic computing; CMOS integrated circuits; CMOS logic circuits; CMOS process; CMOS technology; Circuit faults; Clocks; Frequency; Integrated circuit technology; System-on-a-chip; Voltage;
Conference_Titel :
Very Large Scale Integration, 2006 IFIP International Conference on
Conference_Location :
Nice
Print_ISBN :
3-901882-19-7
DOI :
10.1109/VLSISOC.2006.313257
