Digital phase-locked loop applications to digital radio channels

An all-digital phase-locked loop (DPLL) is used to extract the symbol timing of a 64-QAM signaling scheme over a multipath fading radio channel. The overall transmitter and receiver filter has a raised-cosine pulse shaping characteristic. The receiver structure is composed of a timing recovery system augmented with a DPLL, and a T/2 fractionally-spaced equalizer. A semi-analytic bit error rate technique is used for estimating the symbol error rate of this radio system. The robustness of DPLL is investigated through its implementation on an M56001 DSP chip