Title :
A 1.0 ns 64-bits GaAs adder using quad tree algorithm
Author :
Royannez, Philippe ; Amara, Amara
Author_Institution :
Lab. MASI, Univ. Pierre et Marie Curie, Paris, France
Abstract :
This paper describes a full custom 64-bits adder targeting the VITESSE E/D MESFET process HGaAsIII. This adder which respects a bit slice topology is part of the project of GaAs data-path compiler for ALLIANCE CAD TOOLs. GaAs´s specific properties have been exploited in a full custom approach. Original architecture have been used to increase the parallelism of carries´ computation. The layout is portable using a symbolic approach and could also be used with other E/D MESFET process
Keywords :
III-V semiconductors; MESFET integrated circuits; adders; application specific integrated circuits; field effect logic circuits; gallium arsenide; quadtrees; 1.0 ns; 64 bit; ALLIANCE CAD TOOL; GaAs; HGaAsIII VITESSE E/D MESFET process; bit slice topology; carry complication; data-path compiler; full custom adder; parallel architecture; quad tree algorithm; symbolic portable layout; Arthritis; Binary trees; CMOS logic circuits; Concurrent computing; Costs; Delay; Energy consumption; Equations; Gallium arsenide; Parallel processing;
Conference_Titel :
VLSI, 1996. Proceedings., Sixth Great Lakes Symposium on
Conference_Location :
Ames, IA
Print_ISBN :
0-8186-7502-0
DOI :
10.1109/GLSV.1996.497587
