Title :
High-voltage solutions in standard CMOS
Author :
Santos, P. Mendonça ; Casimiro, A.P. ; Lança, M. ; Simas, M. I Castro
Author_Institution :
Instituto Superior Tecnico, Lisbon, Portugal
fDate :
6/23/1905 12:00:00 AM
Abstract :
This paper presents trends on high-voltage techniques for power integrated circuits, using standard low cost CMOS technologies with no extra processing steps. MOS devices layout specificity towards performance improvement, namely breakdown, parasitic effects and reliability, are emphasized. Comparison with sophisticated and expensive HV technologies reveals CMOS cost-effective for power integration
Keywords :
CMOS integrated circuits; high-voltage techniques; power integrated circuits; CMOS power integrated circuits; MOS devices layout specificity; breakdown; high-voltage techniques; parasitic effects; performance improvement; power integration; reliability; CMOS process; CMOS technology; Costs; Fabrication; Integrated circuit technology; MOS devices; MOSFETs; Power integrated circuits; Power semiconductor switches; Switching circuits;
Conference_Titel :
Power Electronics Specialists Conference, 2001. PESC. 2001 IEEE 32nd Annual
Conference_Location :
Vancouver, BC
Print_ISBN :
0-7803-7067-8
DOI :
10.1109/PESC.2001.954048
