Title :
FPGA-based high performance page layout segmentation
Author :
Ratha, Nalini K. ; Jain, Anil K. ; Rover, Diane T.
Author_Institution :
Dept. of Comput. Sci., Michigan State Univ., East Lansing, MI, USA
Abstract :
A page layout segmentation algorithm for locating text, background and halftone areas is presented. The algorithm has been implemented on Splash 2-an FPGA-based array processor. The speed as determined by the Xilinx synthesis tools projects an application speed of 5 MHz. For documents of size 1,024×1,024 pixels, a significant speedup of two orders of magnitude compared to a SparcStation 20 has been achieved
Keywords :
field programmable gate arrays; image segmentation; parallel processing; 1024 pixel; 5 GHz; FPGA array processor; Splash 2; Xilinx synthesis tool; page layout segmentation algorithm; text; Application specific integrated circuits; Character recognition; Computer architecture; Computer science; Fabrication; Gabor filters; Graphics; Image processing; Image segmentation; Layout;
Conference_Titel :
VLSI, 1996. Proceedings., Sixth Great Lakes Symposium on
Conference_Location :
Ames, IA
Print_ISBN :
0-8186-7502-0
DOI :
10.1109/GLSV.1996.497588
