Abstract :
In the distribution feeder automation systems, to achieve the requirement of 5K–10K data amount between each device within 5ms, the solution of the implementation of FIFO data buffer which is based on CPLD is proposed in this paper. Through analyzing on the FIFO module characteristics, composition and working principle, the FIFO module logic principle diagram based on CPLD is designed, and all of its feature implementations are described using Verilog HDL. At present, the scheme has been applied in the systems of distribution feeder automation, through detecting, which meets the system performance demands.
