Title :
Pipelining of digit-serial processing elements in recursive digital filters
Author :
Karlsson, Magnus ; Vesterbacka, Mark ; Kulesza, Wlodek
Author_Institution :
University of Kalmar
Keywords :
Adders; Arithmetic; Circuits; Clocks; Delay; Digital filters; Energy consumption; Lattices; Pipeline processing; Throughput;
Conference_Titel :
Signal Processing Symposium, 2004. NORSIG 2004. Proceedings of the 6th Nordic
Conference_Location :
Espoo, Finland
Print_ISBN :
951-22-7065-X
