Title :
VLSI delta-sigma cellular neural network for analog random vector generation
Author :
Cauwenberghs, Gert
Author_Institution :
Dept. of Electr. & Comput. Eng., Johns Hopkins Univ., Baltimore, MD, USA
Abstract :
We present a cellular neural network architecture for parallel analog random vector generation, including experimental results from an analog VLSI prototype with 64 channels. Nearest-neighbor coupling between cells produces parallel channels of uniformly distributed random analog values, with statistics that are truly uncorrelated across channels and over time. The cell for each random channel emulates an integrating nonlinearity essentially implementing a delta-sigma modulator, and measures 100 μm×120 μm in 2 μm CMOS technology. Applications include analog encryption and secure communications, analog built-in self-test, stochastic neural networks, and simulated annealing optimization and learning
Keywords :
CMOS analogue integrated circuits; VLSI; analogue processing circuits; built-in self test; cellular neural nets; neural chips; 2 micron; CMOS technology; VLSI; analog encryption; analog random vector generation; built-in self-test; delta-sigma cellular neural network; integrating nonlinearity; nearest-neighbor coupling; parallel channels; secure communications; simulated annealing optimization; stochastic neural networks; Built-in self-test; CMOS technology; Cellular neural networks; Cryptography; Delta modulation; Neural networks; Prototypes; Statistical distributions; Stochastic processes; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-4455-3
DOI :
10.1109/ISCAS.1998.703931
