A mixed analog-digital simulator for ASIC using a novel block tearing approach

Author

Chung, Steve S. ; Bie, Jony L.

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

1993

Firstpage

527

Lastpage

530

Abstract

A mixed-mode simulator for timing verification of analog-digital CMOS VLSI circuits is reported. It was developed by combining SPICE techniques for analog circuit simulation and gate-level techniques for digital circuit simulation based on the event-driven method. A new scheme called the block tearing (BT) approach at the macrocell level is proposed for memory storage savings while preserving reasonable accuracy. Benchmark tests of several example circuits show good performance in terms of speed and accuracy. The simulator is well suited for hierarchial VLSI circuits which are cell-based, such as current ASIC circuit design

Keywords

CMOS integrated circuits; SPICE; VLSI; cellular arrays; circuit analysis computing; discrete event simulation; integrated circuit design; integrated circuit modelling; logic CAD; logic testing; mixed analogue-digital integrated circuits; timing; ASIC circuit design; SPICE; analog-digital CMOS VLSI; block tearing approach; event-driven method; gate-level techniques; macrocell level; memory storage savings; mixed analog-digital simulator; mixed-mode simulator; timing verification; Analog-digital conversion; Application specific integrated circuits; CMOS analog integrated circuits; CMOS memory circuits; Circuit simulation; Circuit testing; Discrete event simulation; SPICE; Timing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-1375-5

Type

conf

DOI

10.1109/ASIC.1993.410774

Filename

410774