Title :
Logic synthesis for testability
Author :
Chien-Chung Tsai ; Marek-Sadowska, M.
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
Abstract :
This paper presents a multilevel logic synthesis method that achieves 100% single stuck-at fault testability. We assume any cell library composed of AND/OR gates. The Fixed Polarity Reed-Muller forms are used to build the initial design. Algebraic factorizations and redundancy removal are two major steps that are used in deriving the final circuit. A predetermined set of input patterns is applied to identify redundancies and serves as the test set for the resulting circuit. Therefore, test pattern generation is not needed. Experimental results show that our method produces circuits with area comparable to Berkeley SIS 1.2.
Keywords :
design for testability; logic design; logic testing; multivalued logic circuits; redundancy; AND gates; Fixed Polarity Reed-Muller form; OR gates; algebraic factorization; circuit design; multilevel logic synthesis; redundancy; single stuck-at fault testability; Binary trees; Boolean functions; Circuit faults; Circuit synthesis; Circuit testing; Libraries; Logic testing; Redundancy; Shape control; Wire;
Conference_Titel :
VLSI, 1996. Proceedings., Sixth Great Lakes Symposium on
Conference_Location :
Ames, IA, USA
Print_ISBN :
0-8186-7502-0
DOI :
10.1109/GLSV.1996.497605
