Title :
A hierarchical approach for power reduction in VLSI chips
Author :
Arunachalam, Prakash ; Abraham, Jacob ; D´Abreu, Manuel
Author_Institution :
Intel Corp., Hillsboro, OR, USA
Abstract :
This paper presents a new mechanism for power analysis and reduction that exploits the hierarchical nature of circuits. A number of mechanisms have been proposed for power reduction, but they do not offer solutions in all cases. An activity-based reduction technique is presented where the clock is turned off for entire modules or sub-modules hierarchically when that portion of the circuit is not in use. Behavioral constraints are used to determine when a portion of the circuit is in use. The method shown is a top-down approach independent of the technology used during fabrication of the chip. Experimental results indicate that this method will result in a considerable reduction in power
Keywords :
VLSI; circuit CAD; digital integrated circuits; integrated circuit design; ATKET; VLSI chips; activity-based reduction technique; behavioral constraints; hierarchical approach; low power design; power reduction; top-down approach; Circuit analysis computing; Circuit simulation; Clocks; Costs; Energy consumption; Integrated circuit interconnections; Jacobian matrices; Packaging; Space exploration; Very large scale integration;
Conference_Titel :
VLSI, 1996. Proceedings., Sixth Great Lakes Symposium on
Conference_Location :
Ames, IA
Print_ISBN :
0-8186-7502-0
DOI :
10.1109/GLSV.1996.497617
