• DocumentCode
    1588574
  • Title

    Memory latency reduction using an address prediction buffer

  • Author

    Billingsley, Arthur ; Fouts, Douglas

  • Author_Institution
    Dept. of Electr. & Comput. Eng., US Naval Postgraduate Sch., Monterey, CA, USA
  • fYear
    1992
  • Firstpage
    78
  • Abstract
    Improving system performance by implementing a memory prediction buffer (MPB) is discussed. The MPB is inserted between the cache and main memory. It predicts the next cache-miss address and prefetches the data. This action decreases main-memory latency and increases system performance
  • Keywords
    buffer storage; memory architecture; performance evaluation; address prediction buffer; cache-miss address; main-memory latency; memory prediction buffer; prefetches; system performance; Application software; Bandwidth; Costs; Delay; Equations; Measurement units; Performance evaluation; Performance gain; Software systems; System performance;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Signals, Systems and Computers, 1992. 1992 Conference Record of The Twenty-Sixth Asilomar Conference on
  • Conference_Location
    Pacific Grove, CA
  • ISSN
    1058-6393
  • Print_ISBN
    0-8186-3160-0
  • Type

    conf

  • DOI
    10.1109/ACSSC.1992.269254
  • Filename
    269254
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1588574