Title :
A memory to read out and write a block of words via one memory access and its application to increase processor and cache performance
Author :
Polkovnikov, Igor
Author_Institution :
San Francisco, CA, USA
Abstract :
A memory architecture for reading out a block of bits, bytes, or words in parallel via one memory access beginning with any address location is presented. Discussed topics are: a processor reading a several-word instruction via one memory access and its comparison with a RISC one; transformation of an existing CISC architecture to a superscalar one reading a set of instructions in parallel; instructions having any size of opcode, immediate data, and address displacement; and a cache updating by several words in parallel
Keywords :
memory architecture; performance evaluation; address displacement; cache; cache performance; memory access; memory architecture; opcode; parallel; processor performance; Art; Image processing; Iterative algorithms; Logic; Memory architecture; Pixel; Read-write memory; Reduced instruction set computing; Shift registers;
Conference_Titel :
Signals, Systems and Computers, 1992. 1992 Conference Record of The Twenty-Sixth Asilomar Conference on
Conference_Location :
Pacific Grove, CA
Print_ISBN :
0-8186-3160-0
DOI :
10.1109/ACSSC.1992.269256
