Lower delay and area efficient non-restoring array divider by using Shannon based adder technique

This paper is mainly focused on designs of full-adder using by Shannon theorem based on pass transistor approach. The proposed Shannon theorem adder, SERF, CMOS 10T and mirror adder circuits are implemented in non-restoring array divider circuit. The divider circuits is schematized by using DSCH2 CAD tools and their layouts are simulated by using Microwind 3 VLSI layout CAD tool. The parameter analyses are analyzed by using BSIM 4 analyzer. The analysis includes power dissipation, propagation delay, chip area, power delay product (PDP), Energy Per Instruction (EPI), latency and throughput. These analyses are compared with reported author results, which shows better improvement in terms of low power, lower area, lower propagation delay and high throughput.