Analysis of combinational cycles in sequential circuits

This paper addresses the analysis of combinational cycles in synchronous, sequential circuits. A circuit that has a combinational cycle does not necessarily have unstable output behavior: the cycle may be “false” for all reachable states and possible input sequences, or the unstable behavior on the cycle may not affect the outputs. We provide a procedure to determine whether a circuit produces a unique, stable output sequence for every input sequence provided by the environment, under all possible circuit delays; such a circuit is called “output-stable”. In addition, if a circuit is determined to be output-stable, then we provide a means of producing an equivalent sequential circuit, without combinational cycles