Regional clock gate splitting algorithm for clock tree synthesis

In this paper, the new clock distribution design flow and algorithm of clock gate splitting to improve the clock gate´s enable signal timing violations had been presented. The clock gate components in a clock tree are exposed to setup timing violations due to the nature that the clock gates skew is normally big as they are located at the beginning of the clock tree. The effective splitting of the clock gate to the lower level of the clock tree will improve the clock gate skew and thus improve the setup margin.