Low complexity CMOS competitive array for approaching assignments

Author

Gomez-Casraneda, F. ; Flores-Nava, Luis M. ; Moreno-Cadenas, José A.

Author_Institution

Center for Res. & Adv. Studies, Mexico City, Mexico

Volume

3

fYear

1998

Firstpage

171

Abstract

This work presents a CMOS analog integrated circuit in which an array of 8×8 winner-take-all neural units or competitive units computes binary matrices as an approach to the solution of assignment problems. The small silicon area in this system results from using early low-complexity current-mode circuits. The dynamic performance for selecting winning units by this prototype analog integrated circuit that encodes permutation matrices is evaluated with PSpice simulations

Keywords

CMOS analogue integrated circuits; SPICE; analogue processing circuits; matrix algebra; neural chips; optimisation; CMOS analog integrated circuit; PSpice simulation; assignment problem; binary matrix; competitive array; low-complexity current-mode circuit; permutation matrix; silicon area; winner-take-all neural unit; Computer architecture; Computer networks; Concurrent computing; Cost function; High performance computing; Linear matrix inequalities; Silicon; Space technology; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on

Conference_Location

Monterey, CA

Print_ISBN

0-7803-4455-3

Type

conf

DOI

10.1109/ISCAS.1998.703940

Filename

703940