DocumentCode
1589505
Title
Deeply Pipelined DSP Solution to Key Modules in H. 264
Author
Zhu, Jinxiu ; Cao, Ning ; Chen, Yushan ; Li, Guozuan
fYear
2008
Firstpage
107
Lastpage
112
Abstract
With the rapid development of microprocessor, embedded multimedia products are gradually becoming the mainstream in the market. However, the high coding efficiency enabled by the H.264 video compression standard comes with substantially greater algorithmic complexity as compared to that of existing standards. And this additional complexity results in many difficulties in the implementation and optimization tasks. This paper analyzes the algorithms of the two time-consuming modules of integer transform and motion estimation in H.264. Then optimizes the two modules based on the extended instruction set of C64x/C64x+. Finally, deeply pipelined DSP solutions to two modules are presented in this paper. The experiment results show that optimizing parallel assembly can make the codes more efficient.
Keywords
Digital signal processing; Embedded computing; DM647; H.264; ICT; motion estimation; optimizing parallel assembly; pipeline;
fLanguage
English
Publisher
ieee
Conference_Titel
Embedded Computing, 2008. SEC '08. Fifth IEEE International Symposium on
Conference_Location
Beijing
Print_ISBN
978-0-7695-3348-3
Type
conf
DOI
10.1109/SEC.2008.44
Filename
4690733
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