A low-power 17-GHz 256/257 dual-modulus prescaler fabricated in a 130-nm CMOS process

A divide-by 256/257 dual-modulus prescaler has been fabricated in a 130-nm CMOS process. The synchronous divide-by-4/5 divider uses source coupled logic (SCL) D flip-flops with a resistive load to achieve the 17.2-GHz maximum operating frequency at an input power of 0 dBm, The prescaler requires 4.3 mA current from a 1.5-V supply. This circuit has the highest operating frequency and the lowest power consumption reported to date among CMOS dual-modulus prescalers that can operate at 10 GHz or higher. The prescaler also works up to 15.8 GHz with a 1.2-V supply and draws 3-mA current.