• DocumentCode
    1589530
  • Title

    IDD scan test method for fault localization technique on CMOS VLSI failure analysis

  • Author

    Abdullah, Farisal ; Nayan, Nafarizal ; Jamil, M.M.A. ; Kamsin, Norfauzi

  • Author_Institution
    Fac. of Electr. & Electron. Eng., Univ. Tun Hussein Onn Malaysia, Batu Pahat, Malaysia
  • fYear
    2010
  • Firstpage
    104
  • Lastpage
    107
  • Abstract
    One of the fashionable stress test that has been practiced in CMOS VLSI recently is known as IDDQ scan test. It has competency to be exercised as a part of failure analysis method in localization latent defect with nano scale geometry, i.e. gate oxide hole. An extension study in this field delivers proficiency on logic circuit diagnostic. Form the results obtained during the experiment, it shows that the IDD scan test can be applied effectively in triggering significant emission spot during anomalous logic transition.
  • Keywords
    CMOS integrated circuits; VLSI; failure analysis; fault location; integrated circuit testing; CMOS VLSI failure analysis; IDD scan test method; fault localization; gate oxide hole; localization latent defect; logic circuit diagnostic; nano scale geometry; CMOS logic circuits; CMOS technology; Circuit faults; Circuit simulation; Circuit testing; Failure analysis; Integrated circuit testing; Logic circuits; Logic design; Logic testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Semiconductor Electronics (ICSE), 2010 IEEE International Conference on
  • Conference_Location
    Melaka
  • Print_ISBN
    978-1-4244-6608-5
  • Type

    conf

  • DOI
    10.1109/SMELEC.2010.5549409
  • Filename
    5549409
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1589530