Time-to-digital converter for RF frequency synthesis in 90 nm CMOS

Author

Staszewski, Robert Bogdan ; Vemulapalli, Sudheer ; Vallur, Prasant ; Wallberg, John ; Balsara, Poras T.

Author_Institution

Wireless Analog Technol. Center, Texas Instrum. Inc., Dallas, TX, USA

fYear

2005

Firstpage

473

Lastpage

476

Abstract

We propose and demonstrate a 20 ps time-to-digital converter (TDC) in 90 nm digital CMOS. It is used as a phase/frequency detector and charge pump replacement in an all-digital PLL for a fully-compliant GSM transceiver. The TDC core is based on a pseudo-differential digital architecture that makes it insensitive to NMOS and PMOS mismatches. The time conversion resolution is equal to an inverter propagation delay, which is the finest logic-level regenerative timing in CMOS. The TDC is self calibrating with estimation accuracy better than 1%. Measured INL is 0.7 LSB. The TDC consumes 1.3 mA from a 1.3 V supply.

Keywords

CMOS digital integrated circuits; calibration; cellular radio; delays; digital phase locked loops; flip-flops; frequency synthesizers; integrated circuit design; logic design; logic gates; phase detectors; timing; transceivers; 1.3 V; 1.3 mA; 20 ps; 90 nm; GSM transceiver; NMOS mismatch; PMOS mismatch; RF frequency synthesis; all-digital PLL; charge pump replacement; digital CMOS; estimation accuracy; flip-flops; frequency detector; inverter propagation delay; inverters; logic-level regenerative timing; phase detector; pseudo-differential digital architecture; time conversion resolution; time-to-digital converter; Charge pumps; Frequency conversion; Frequency synthesizers; GSM; MOS devices; Phase detection; Phase frequency detector; Phase locked loops; Radio frequency; Transceivers;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency integrated Circuits (RFIC) Symposium, 2005. Digest of Papers. 2005 IEEE

ISSN

1529-2517

Print_ISBN

0-7803-8983-2

Type

conf

DOI

10.1109/RFIC.2005.1489847

Filename

1489847