Graph and information based intelligent design for testability

The cost effectiveness of fault detection and isolation techniques used in complex systems is paid more attention in nowadays. Well design for testability (DFT) can save cost in fault detection and isolation, assure adequate failure coverage by Built-In Test (BIT) and Automatic Test Equipment (ATE), reduce false alarms, and reduce maintenance training requirements. However, there are limited intelligent approaches implemented and applied for DFT for integrated diagnostics. Meanwhile, different tools for DFT are incompatible with each other. This phenomenon has prevented testability engineering from integrating into system engineering. The paper promotes a general-purpose graph and information based intelligent approach to DFT supporting concurrent system engineering. Testability models, including information flow model, multi-signal flow model, hybrid dependency model, etc, can all be described by a graph theory core with information attached. Meanwhile, intelligent algorithms are imported to solve complex testability inference problems, most of which are NP problems. The testability figures of merit (TFOMs) defined in IEEE 1522 are adopted to standardize the quantitative parameters to assess the testability level. An intelligent DFT framework is constructed according to AI-ESTATE to realize artificial intelligent information exchanges. The graph and information based intelligent approach is shown to be efficient and effective to realize advanced DFT of complex large systems. The transitive closure algorithm and the logical closure algorithm given in the paper is verified by the example of an electronic equipment with 4 test items and 5 fault modes. The genetic algorithms (GAs) based fault detection rate (FDR) allocation method is applied in a 3 layers´ certain electronic system composed of 6 subsystems. By comparing with experience and fault rate based TFOMs allocation method, GAs is shown to be more adaptive and efficiency.