The need for co-simulation in ASIC-verification

We present a new ASIC design process including software/hardware co-simulation. The increasing complexity of software/hardware systems means that the design process takes more time and today the verification is often the bottle neck in the design process. For example, synthesis tools have drastically reduced the design time for ASICs and therefore the verification now occupies a larger proportion of the entire design process time. In many software/hardware applications co-simulation can considerably reduce the verification time for the ASIC. This article describes and discusses today´s verification methods and describes the new co-simulation design process for ASICs.