DocumentCode
1590238
Title
The Design of a Cycle Accurate Multi-core Architecture Performance Simulator
Author
Wang, Gang ; Tiefei, Zhang ; Yan, Like ; Bin, Xie ; Chen, Tianzhou
Author_Institution
Coll. of Comput. Sci., Zhejiang Univ., Hangzhou
fYear
2008
Firstpage
282
Lastpage
287
Abstract
As multi-core technology has become the trend to improve the performance of processor, there is more need to design a performance simulator for the design of multi-core architecture and for the evaluation of system performance. However there are few simulators that support different architectures of multi-core processor well. This paper presents a design and implementation of a cycle accurate multi-core processor architecture simulator, it is a component design, which can be customized to different multi-core architectures, furthermore, provides a practical tool for the design and evaluation of multi-core architecture.
Keywords
performance evaluation; program processors; multicore architecture; multicore technology; processor performance; system performance evaluation; Computational modeling; Computer architecture; Computer science; Computer simulation; Educational institutions; Embedded computing; Hardware; Multicore processing; System performance; Technological innovation;
fLanguage
English
Publisher
ieee
Conference_Titel
Embedded Computing, 2008. SEC '08. Fifth IEEE International Symposium on
Conference_Location
Beijing
Print_ISBN
978-0-7695-3348-3
Type
conf
DOI
10.1109/SEC.2008.19
Filename
4690763
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