Implementation of a LMS filter on FPGA employing extremeDSP and smart IP-core design

Field Programmable Gate Arrays have become popular platform for digital signal processing, however, the conventional method, which is essentially writing a source code in a hardware description language to design a product on a FPGA, is time consuming and complicated. This restricts the implementation of complex signal processing algorithm on FPGA. In this paper, two fast design methods of algorithm implementation on FPGA were proposed: ExtremeDSP solution and Smart IP-Core technology. The AccelDSP Synthesis tool, as the main component of ExtremeDSP solution allows transferring a MATLAB floating point design into a hardware module that can be implemented on a Xilinx FPGA. Employing predefined cores can cut the design time and significantly reduce risk while having access to the best performing and lowest cost component available. Implementation of a LMS-adaptive filter employing these two methods has been achieved and the simulation results indicate that both of the two fast designs have high performance.