High frequency noise optimization of sub-100 nm MOSFETs utilizing three dimensional TCAD simulation

High frequency noise issues with scaled MOSFETs are calculated and analyzed for the purpose of structure optimization utilizing a three dimensional TCAD device simulator, and the following results have been revealed: for the transistors with a gate length less than 100 nm, the induced gate noise becomes very sensitive to the gate width because of the higher gate resistance; the gate noise originated from gate resistance for sub-100 nm MOSFETs also increases to the level comparable to the induced gate noise; the current concentration by the divot shape between the edge of the gate and STI makes all of the channel noise, induced gate noise, and NFmin worse. These results have shown the possibility of using TCAD for the analysis of the high frequency noise.