A high speed, real-to-quadrature converter with filtering and decimation

Author

Desormeaux, L. ; Szwarc, V. ; Lodge, J.

fYear

1996

Firstpage

252

Lastpage

255

Abstract

The design of a high speed, real-to-quadrature converter chip set with filtering, decimation, built-in self-test (BIST), and IEEE 1149.1 based boundary scan will be presented. The 15,000 gate application specific integrated circuit (ASIC) implemented in 1.5 μm CMOS gate array technology has 3 half-band filters with 3, 7, and 11 taps which can be cascaded in a number of combinations. The intended ASIC application is the processing of narrowband radio signals at IF frequencies. The paper addresses the ASIC´s functionality, VLSI implementation and test methodology, and provides both simulation and test data

Keywords

CMOS digital integrated circuits; VLSI; application specific integrated circuits; boundary scan testing; built-in self test; convertors; digital filters; digital signal processing chips; integrated circuit testing; 1.5 micron; ASIC; CMOS gate array; IEEE 1149.1 boundary scan test; IF signal; VLSI chip; built-in self-test; cascaded half-band filters; decimation; filtering; high speed real-to-quadrature converter; radio signal processing; Application specific integrated circuits; Built-in self-test; CMOS technology; Filtering; Filters; Integrated circuit technology; Narrowband; RF signals; Signal processing; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 1996. Proceedings., Sixth Great Lakes Symposium on

Conference_Location

Ames, IA

ISSN

1066-1395

Print_ISBN

0-8186-7502-0

Type

conf

DOI

10.1109/GLSV.1996.497628

Filename

497628