A CMOS VLSI implementation of an N×N multiplexing circuitry for ATM applications

Author

Rizkalla, Maher E. ; Aldridge, Richard L. ; Khan, Nadeem A. ; Gundrum, Harry C.

Author_Institution

Dept. of Electr. Eng., Purdue Univ., Indianapolis, IN, USA

fYear

1996

Firstpage

256

Lastpage

259

Abstract

A non internal blocking ATM packet switching network using CMOS technology has been developed for an N×N switch. A multiplexing circuitry with 32 inputs was designed and implemented using simple logic gates. The development has utilized an interconnection network of 1×32 parallel expander circuits. The control unit consisting of serial shift registers and latches to keep the destination path open for the length of the packet, were designed using MAGIC software and simulated by IRSIM. As low as 5 ns delay was estimated by the 1×32 expander circuit, while the clock generated by the combinational circuit for latching showed a delay of 190 ns. The system has been fabricated using MOSIS services, and as minimum of 5 ns delay was measured between the input and output nodes of the switching circuit

Keywords

CMOS logic circuits; VLSI; asynchronous transfer mode; delays; multiplexing; multiplexing equipment; multistage interconnection networks; packet switching; shift registers; 5 ns; ATM applications; CMOS VLSI implementation; IRSIM; MAGIC software; MOSIS services; N×N multiplexing circuitry; combinational circuit; delay; destination path; interconnection network; latches; latching; logic gates; packet switching network; parallel expander circuits; serial shift registers; switching circuit; Asynchronous transfer mode; CMOS logic circuits; CMOS technology; Delay estimation; Logic circuits; Logic design; Logic gates; Packet switching; Switches; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 1996. Proceedings., Sixth Great Lakes Symposium on

Conference_Location

Ames, IA

ISSN

1066-1395

Print_ISBN

0-8186-7502-0

Type

conf

DOI

10.1109/GLSV.1996.497629

Filename

497629