DocumentCode
159094
Title
A multi-core version of FreeRTOS verified for datarace and deadlock freedom
Author
Chandrasekaran, Prakash ; Shibu Kumar, K.B. ; Minz, Remish L. ; D´Souza, Deepak ; Meshram, Lomesh
Author_Institution
Dept. of Comput. Sci. & Autom., Indian Inst. of Sci., Bangalore, India
fYear
2014
fDate
19-21 Oct. 2014
Firstpage
62
Lastpage
71
Abstract
We present the design of a multicore version of FreeRTOS, a popular open source real-time operating system for embedded applications. We generalize the scheduling policy of FreeRTOS to schedule the n highest-priority longest-waiting tasks, for an n-core processsor. We use a locking mechanism that provides maximum decoupling between tasks, while ensuring mutually exclusive access to kernel data-structures. We provide an implementation of the portable part of FreeRTOS (written in C) and provide the device specific implementation of the locking mechanism for Intel and ARM Cortex multicore processors. We model the locking mechanism and the locking protocol used by the API´s in the Spin model-checking tool and verify that the design is free from dataraces and deadlocks. Finally, we extend the existing FreeRTOS Windows simulator to simulate our multicore version of FreeRTOS, and evaluate its performance on some demo applications.
Keywords
application program interfaces; data structures; embedded systems; formal verification; multiprocessing systems; operating system kernels; performance evaluation; processor scheduling; public domain software; API; ARM Cortex multicore processor; C language; FreeRTOS Windows simulator; Intel multicore processor; Spin model-checking tool; datarace freedom; deadlock freedom; device specific implementation; embedded applications; highest-priority longest-waiting tasks; kernel data-structures; locking mechanism; locking protocol; maximum task decoupling; multicore FreeRTOS; mutually exclusive access; open source real-time operating system; performance evaluation; scheduling policy; Data structures; Kernel; Multicore processing; Program processors; Schedules; System recovery;
fLanguage
English
Publisher
ieee
Conference_Titel
Formal Methods and Models for Codesign (MEMOCODE), 2014 Twelfth ACM/IEEE International Conference on
Conference_Location
Lausanne
Type
conf
DOI
10.1109/MEMCOD.2014.6961844
Filename
6961844
Link To Document