Title :
Force-observe, a new design for testability approach (CMOS VLSI circuits)
Author :
Savaria, Yvon ; Kaminska, Bozena
Author_Institution :
Dept. of Electr. Eng., Ecole Polytech. de Montreal, Que., Canada
Abstract :
A technique called the force-observe approach (F-O) for eliminating hard-to-test or untestable nodes in CMOS technology is presented. This technique requires the addition of controllable and observable nodes to a circuit to improve the fault coverage as much as required. The F-O approach is characterized by a speed degradation smaller than the one introduced by other techniques. A formula to evaluate the area overhead of the F-O approach is proposed. It is shown that the area overhead is small for a complex VLSI circuit with a limited number of testability problems. This approach is very promising and, used in conjunction with the scan chain technique, it can be developed into a comprehensive solution to the problem of eliminating hard-to-test or untestable nodes from large VLSI designs.<>
Keywords :
CMOS integrated circuits; VLSI; integrated circuit technology; integrated circuit testing; integrated logic circuits; logic design; logic testing; CMOS technology; VLSI designs; area overhead; complex VLSI circuit; controllable nodes; design for testability; fault coverage; force-observe approach; logic circuits; observable nodes; scan chain technique; speed degradation; untestable node elimination; CMOS technology; Circuit faults; Circuit testing; Degradation; Design for testability; Hardware; Logic testing; Sequential analysis; System testing; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1988., IEEE International Symposium on
Conference_Location :
Espoo, Finland
DOI :
10.1109/ISCAS.1988.14899
