• DocumentCode
    159120
  • Title

    Formal property verification in a conformance testing framework

  • Author

    Abbas, Haider ; Mittelmann, Hans ; Fainekos, Georgios

  • Author_Institution
    Sch. of Electr., Energy & Comput. Eng., Arizona State Univ., Tempe, AZ, USA
  • fYear
    2014
  • fDate
    19-21 Oct. 2014
  • Firstpage
    155
  • Lastpage
    164
  • Abstract
    In model-based design of cyber-physical systems, such as switched mixed-signal circuits or software-controlled physical systems, it is common to develop a sequence of system models of different fidelity and complexity, each appropriate for a particular design or verification task. In such a sequence, one model is often derived from the other by a process of simplification or implementation. E.g. a Simulink model might be implemented on an embedded processor via automatic code generation. Three questions naturally present themselves: how do we quantify closeness between the two systems? How can we measure such closeness? If the original system satisfies some formal property, can we automatically infer what properties are then satisfied by the derived model? This paper addresses all three questions: we quantify the closeness between original and derived model via a distance measure between their outputs. We then propose two computational methods for approximating this closeness measure. Finally, we derive syntactical re-writing rules which, when applied to a Metric Temporal Logic specification satisfied by the original model, produce a formula satisfied by the derived model. We demonstrate the soundness of the theory with several experiments.
  • Keywords
    embedded systems; formal specification; formal verification; program compilers; temporal logic; automatic code generation; conformance testing framework; cyber-physical systems; embedded processor; formal property verification; metric temporal logic specification; model-based design; Computational modeling; Educational institutions; Integrated circuit modeling; Measurement; Software packages; Switches; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Formal Methods and Models for Codesign (MEMOCODE), 2014 Twelfth ACM/IEEE International Conference on
  • Conference_Location
    Lausanne
  • Type

    conf

  • DOI
    10.1109/MEMCOD.2014.6961854
  • Filename
    6961854