Iris Biometic Processor Enhanced Module FPGA-Based Design

Iris Identification is nowadays one of the most promising techniques in Authentication. Most modern iris recognition systems are currently deployed on traditional sequential digital systems, such as a simple DSPs or MIPS processor. However, in this method, we can only match each data one by one, which will waste much time. In this study, iris matching, a repeatedly executed portion of a modern iris recognition algorithm is parallelized on an FPGA system. We demonstrate a 22 times speedup of the parallelized algorithm on the FPGA system when compared to a simple DSPs.