A simultaneous placement and global routing algorithm for an FGPA with hierarchical interconnection structure

An efficient layout design algorithm is presented. The algorithm simultaneously perform the placement and the global routing for the design of using FPGA with hierarchical interconnection structure (HFPGA). It is based on a k-way min-cut placement technique. The min-cut technique generates a partitioning tree which is then used to assign logic blocks to realize the function of modules in the netlist. The partitioning tree is also used to find the routing paths of interconnections between the logic blocks. Investigation is performed experimentally by implementing a set of industrial circuits using the algorithm