Title :
On verifying the correctness of retimed circuits
Author :
Huang, Shi-Yu ; Cheng, Kwang-Ting ; Chen, Kuang-Chien
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
Abstract :
We address the problem of verifying a retimed circuit. After retiming, some latches in a sequential circuit are repositioned to reduce the clock cycle time and thus the behavior of the combinational portion is changed. Here, we present a novel approach to check the correctness of a retimed circuit according to the definition of 3-valued equivalence. This approach is based on our verification framework using sequential ATPG techniques. We further incorporate an algorithm to pre-process the circuits and make the verification process even more efficient. We will present the experimental results of verifying the retimed circuits with hundreds of flip-flops on ISCAS89 benchmark circuits to show its capability
Keywords :
automatic testing; clocks; flip-flops; integrated circuit testing; logic testing; sequential circuits; ISCAS89 benchmark circuits; clock cycle time; correctness verification; flip-flops; retimed circuits; sequential ATPG techniques; sequential circuit; three-valued equivalence; verification framework; Automatic test pattern generation; Boolean functions; Circuit simulation; Clocks; Data structures; Formal verification; Latches; Logic circuits; Sequential circuits; State-space methods;
Conference_Titel :
VLSI, 1996. Proceedings., Sixth Great Lakes Symposium on
Conference_Location :
Ames, IA
Print_ISBN :
0-8186-7502-0
DOI :
10.1109/GLSV.1996.497633
