On double transition faults as a delay fault model

We define a new delay fault model, called the double transition fault model. Under this model, a fault is associated with a pair of lines and a pair of transitions on these lines. The model captures the effects of defects that increase the delays of two (or more) individual lines by an amount that causes the circuit to fail when signals are propagated through both lines. It thus provides a simplification of the path delay fault model, that does not suffer from the exponential behavior of this model. We propose a test generation procedure for double transition faults, based on reordering of a given test set for stuck-at faults. The procedure does not require enumeration of all double transition faults, and is thus applicable to circuits with large numbers of lines. We present experimental results of this procedure for several benchmark circuits