DocumentCode :
1592262
Title :
Improving circuit testability by clock control
Author :
Einspahr, Kent L. ; Seth, Sharad C. ; Agrawal, Vishwani D.
Author_Institution :
Dept. of Comput. Sci., Concordia Univ., Seward, NE, USA
fYear :
1996
Firstpage :
288
Lastpage :
293
Abstract :
The testability of a sequential circuit can be improved by controlling the clock of individual storage elements during testing. We propose several clock control strategies derived from an analysis of the circuit, its S-graph structure, and its function. Through examples we show how the number of clocks affects the circuit´s testability. It is shown that if certain flip-flops (FFs) are scanned (or otherwise initialized), the remaining FFs can be controlled and initialized to any arbitrary state using the clock control. We derive a controllability graph and use it to assign clocks to FFs and to schedule the clocks to set the FFs to an arbitrary state during test. Our analysis of sequential benchmark circuits indicates that this could be an attractive scheme for combining partial scan with clock control
Keywords :
clocks; flip-flops; integrated circuit testing; logic testing; sequential circuits; signal flow graphs; S-graph structure; arbitrary state; circuit testability; clock control; controllability graph; flip-flops; individual storage elements; partial scan; sequential benchmark circuits; sequential circuit; testability; Benchmark testing; Circuit analysis; Circuit testing; Clocks; Computer science; Educational institutions; Flip-flops; Hardware; Sequential analysis; Sequential circuits;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI, 1996. Proceedings., Sixth Great Lakes Symposium on
Conference_Location :
Ames, IA
ISSN :
1066-1395
Print_ISBN :
0-8186-7502-0
Type :
conf
DOI :
10.1109/GLSV.1996.497635
Filename :
497635
Link To Document :
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