Title :
Fault-tolerant array processors: an approach based upon A*N codes
Author_Institution :
Dept. of Electron., Politecnico di Milano, Italy
Abstract :
A novel approach to online error detection in bit-parallel array processors by means of A*N coding is presented. The optimal choice of such codes is discussed. Some methodologies to design array processors with high error detection capability, low silicon area consumption, and low computational overhead are proposed and evaluated
Keywords :
digital arithmetic; error correction codes; error detection; fault tolerant computing; microprocessor chips; parallel architectures; A*N coding; arithmetic array architecture; bit-parallel array processors; high error detection capability; low computational overhead; low silicon area consumption; online error detection; Circuit faults; Computer architecture; Concurrent computing; Error correction; Fault detection; Fault tolerance; Physics computing; Redundancy; Silicon; System testing;
Conference_Titel :
Circuits and Systems, 1988., IEEE International Symposium on
Conference_Location :
Espoo
DOI :
10.1109/ISCAS.1988.14900
