Title :
Testable design environment with test-added tools
Author :
Liou, Yih-June ; Wu, Wei-Shiou ; Chi, Mely Chen
Author_Institution :
Design Autom. Dev. Dept., Ind. Technol. Res. Inst., Chutung, Hsinchu, Taiwan
Abstract :
A testable design environment with test-added tools is presented. These programs check whether the circuit design violates testable rules, locate the sources of poor testability, and calculate toggle rate of the circuit. A testable design flow is introduced and functions of the programs are described. The system is in production use and some experimental results are also shown
Keywords :
application specific integrated circuits; automatic test software; circuit CAD; design for testability; fault diagnosis; hardware description languages; integrated circuit testing; logic CAD; logic testing; ASIC; Verilog HDL; design for testability; logic circuit testability; sequential ATPG; sources of poor testability; test-added tools; testable design environment; testable design flow; toggle rate; Circuit faults; Circuit testing; Controllability; Design automation; Design for testability; Hardware design languages; Integrated circuit testing; Logic testing; Observability; System testing;
Conference_Titel :
ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-1375-5
DOI :
10.1109/ASIC.1993.410806
