Title :
A New Salicidation Process with Solid Antimony (Sb) Segregation (SSbS) for Achieving Sub-0.1 eV Effective Schottky Barrier Height and Parasitic Series Resistance Reduction in N-Channel Transistors
Author :
Wong, Hoong-Shing ; Koh, Alvin Tian-Yi ; Chin, Hock-Chun ; Lee, Rinus Tek-Po ; Chan, Lap ; Samudra, Ganesh ; Yeo, Yee-Chia
Author_Institution :
Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore (NUS), Singapore
Abstract :
We report a new CMOS-compatible salicidation process to achieve sub-0.1 eV effective Schottky barrier (SB) height for NiSi/n-Si, one of the lowest values reported-to-date, and its device integration for contact resistance reduction in n-FETs. A thin solid Antimony (Sb) layer is inserted beneath Ni prior to S/D silicidation, acting as a large source of n-type dopants. After silicidation, a very high concentration of Sb is incorporated at the NiSi/Si interface. This solid Sb segregation (SSbS) process reduces the effective SB height and parasitic series resistance. The SSbS process leads to enhanced n-FET performance without degradation in off-state leakage.
Keywords :
CMOS integrated circuits; Schottky barriers; antimony; contact resistance; elemental semiconductors; field effect transistors; nickel alloys; segregation; semiconductor doping; silicon; silicon alloys; CMOS-compatible salicidation; N-channel transistors; NiSi-Si; Sb; Schottky barrier height; device integration; field effect transistors; n-FETs; n-type dopants; off-state leakage; parasitic series contact resistance reduction; solid antimony segregation; Amplitude modulation; CMOS technology; Contact resistance; Electric resistance; Schottky barriers; Silicidation; Silicon; Solids; Temperature measurement; Wet etching;
Conference_Titel :
VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4244-1614-1
Electronic_ISBN :
1524-766X
DOI :
10.1109/VTSA.2008.4530787
