Title :
Periphery Scaling Challenges for NVM
Author :
Brand, Adam ; Dutta, Ranadeep ; Ma, Sean ; Banerjee, Robi
Author_Institution :
Intel Corp., Santa Clara, CA
Abstract :
In each generation of non-volatile memory (NVM) technology, higher periphery transistor density is desired, but the operating voltage requirement tends to stay constant or rise. Technology constraints to deliver fixed voltage scaling are considered, including Lg scaling, contact size reduction and BVD (Drain breakdown voltage) improvement. Junction optimization is extending the planar technology to the 45 nm node. Asymmetric, FinFet, and recessed channel (RC) devices are considered for use in the future NVM periphery, and RC offers the best opportunity to scale device area while delivering high BVD.
Keywords :
random-access storage; scaling circuits; transistors; BVD; NVM; RC; contact size reduction; drain breakdown voltage; fixed voltage scaling; nonvolatile memory technology; recessed channel devices; transistor density; Breakdown voltage; Charge pumps; Circuit topology; Decoding; Educational institutions; FinFETs; Implants; Logic devices; MOS devices; Nonvolatile memory;
Conference_Titel :
VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4244-1614-1
Electronic_ISBN :
1524-766X
DOI :
10.1109/VTSA.2008.4530791
