The effect of gate oxide thickness and drain bias on NBTI degradation in 45nm PMOS

This paper presents the effects of gate oxide scaling and drain bias variation on the Negative Bias Temperature Instabilities (NBTI) of a 45nm PMOSFET. The gate oxide thickness parameter is varied in this work at values of 1.8nm, 2nm and 3nm. The drain bias of the PMOS is also varied, at values 50mV and 1.2V, in order to observe its effect on the NBTI of the PMOS. The effects on the fundamental device parameters namely the interface trap concentration, threshold voltage and drain current had been studied utilizing the technology CAD (TCAD) Sentaurus Synopsys simulator. At decreasing gate oxide thickness, the PMOS transistor presents a higher interface trap concentration but exhibits improvement in the threshold voltage shift and less degradation in the drain current, when a high stress temperature and large negative bias are applied. In addition to that, the stressed transistor would exhibit significant current degradation at a higher drain bias.