Title :
Enabling technologies for 3D chip stacking
Author :
Leduc, Patrick ; Cioccio, Lea Di ; Charlet, Barbara ; Rousseau, Maxime ; Assous, Myriam ; Bouchu, David ; Roule, Anne ; Zussy, Marc ; Gueguen, Pierric ; Roman, Antonio ; Rozeau, Olivier ; Heitzmann, Michel ; Nieto, Jean-Pierre ; Vandroux, Laurent ; Haumes
Author_Institution :
CEA-Leti Minatec, Grenoble
Abstract :
This paper presents several key technologies developed for high density 3D integration by circuit stacking, i.e. with an inter-strata connection pitch lower than 10 mum. Direct bonding technology, die-to-wafer self-assembly, wafer thinning process and copper TSV process are discussed. 2 mum to 5 mum large copper TSV chains are presented with a TSV resistance <200 mOmega. Substrate noise due to TSV is also considered by TCAD and SPICE simulations in order to define preliminary design rules.
Keywords :
SPICE; integrated circuit design; self-assembly; wafer bonding; 3D chip stacking; 3D integration; Cu; SPICE simulation; TCAD simulation; TSV process; bonding technology; circuit stacking; die-to-wafer self-assembly; wafer thinning; Annealing; Copper; Integrated circuit interconnections; Self-assembly; Stacking; Surface topography; Temperature; Thermal resistance; Through-silicon vias; Wafer bonding;
Conference_Titel :
VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4244-1614-1
Electronic_ISBN :
1524-766X
DOI :
10.1109/VTSA.2008.4530806
