Title :
A 45nm NOR Flash Technology with Self-Aligned Contacts and 0.024μm2 Cell Size for Multi-level Applications
Author :
Fastow, R. ; Banerjee, R. ; Bjeletich, P. ; Brand, A. ; Chao, H. ; Gorman, J. ; Guo, X. ; Heng, J.B. ; Koenigsfeld, N. ; Ma, S. ; Masad, A. ; Soss, S. ; Woo, B.J.
Author_Institution :
Intel Corp., Santa Clara, CA
Abstract :
A 45nm NOR flash technology featuring a self aligned contact ETOX architecture is demonstrated on a 1 Gbit MLC product having a die area of 30.05mm2. The cell size of 0.024μm2 is the smallest NOR cell reported to date and is manufactured entirely with dry lithography tools. With an aggressively scaled drain space of 100nm and gate length of 110nm, the cell shows robust short channel behavior, and excellent cycling behavior.
Keywords :
NOR circuits; flash memories; lithography; NOR flash memory; dry lithography tools; memory size 1 GByte; self aligned contact ETOX architecture; short channel behavior; size 100 nm to 110 nm; size 45 nm; Educational institutions; Flash memory; Implants; Lithography; Manufacturing; Plugs; Rails; Robustness; Space technology; Tungsten;
Conference_Titel :
VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4244-1614-1
Electronic_ISBN :
1524-766X
DOI :
10.1109/VTSA.2008.4530808
