Title :
Drain Read Disturb Assessment of NOR Flash Memory
Author :
Lee, Yung-Huei ; Mielke, Neal ; McMahon, William ; Lu, Yin-Lung R. ; Meng, Qingru ; Jiang, Linda
Author_Institution :
Intel Corp., Santa Clara, CA
Abstract :
Drain read disturb (RD) is becoming an intrinsic reliability concern for NOR flash scaling and MLC operation. A drain RD time-to-error model has been generated which takes into consideration the voltage dependence, read cycling, and Poisson random statistics. This model can be used to optimize the circuit read timing design and to assess process improvement to ensure that products meet the customer spec and lifetime usage.
Keywords :
NOR circuits; Poisson distribution; flash memories; reliability; NOR flash memory; Poisson random statistics; circuit read timing design; drain read disturb assessment; multilevel cell operation; reliability; Circuits; Degradation; Design optimization; Educational institutions; Electrons; Flash memory; Phased arrays; Statistics; Timing; Voltage;
Conference_Titel :
VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4244-1614-1
Electronic_ISBN :
1524-766X
DOI :
10.1109/VTSA.2008.4530809
