Drain Read Disturb Assessment of NOR Flash Memory

Drain read disturb (RD) is becoming an intrinsic reliability concern for NOR flash scaling and MLC operation. A drain RD time-to-error model has been generated which takes into consideration the voltage dependence, read cycling, and Poisson random statistics. This model can be used to optimize the circuit read timing design and to assess process improvement to ensure that products meet the customer spec and lifetime usage.